thunk / The Bench

The Bench

This is the traffic your driver put on the bus. The same init sequence M3 and M4 taught - reset, wake, color mode, window, then the pixel stream - drove a simulated ILI9341, and the panel below is what its framebuffer holds. Nothing here is a picture of a screen; it is the decoded result of 153620 bus events.

240 x 320, decoded from the recorded trace by the panel model.

The bus trace, annotated

Every event on the wire, as a logic analyzer would group it: select edges, named commands, and data runs folded to one row each.
kind	row
select	v (transaction begins)
cmd	01 SWRESET (reset)
cmd	11 SLPOUT (wake)
cmd	3A COLMOD (16-bit color)
data	55
cmd	29 DISPON (display on)
select	^ (transaction ends)
select	v (transaction begins)
cmd	2A CASET (column window)
data	00 00 00 EF
cmd	2B PASET (page window)
data	00 00 01 3F
cmd	2C RAMWR (pixel stream follows)
data	FD C3 BD DF BD DF BD DF ... (153600 bytes)
select	^ (transaction ends)

One byte on the wire

RAMWR (0x2C), the command that opens the pixel stream, exactly as the M3 lesson drew it - MSB first, data settled before each rising clock edge:

bit    0   0   1   0   1   1   0   0 
clk  _/\__/\__/\__/\__/\__/\__/\__/\_
data ________/~~~\___/~~~~~~~\_______